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| ? 2008 microchip technology inc. ds21202h-page 1 24c02c features: ? single-supply with operat ion from 4.5v to 5.5v ? low-power cmos technology: - read current 1 ma, typical - standby current 10 a, typical ? 2-wire serial interface, i 2 c compatible ? cascadable up to eight devices ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz and 400 khz clock compatibility ? fast page or byte write time 1 ms, typical ? self-timed erase/write cycle ? 16-byte page write buffer ? hardware write-protect for upper half of the array (80h-ffh) ? esd protection >4,000v ? more than 1 million erase/write cycles ? data retention >200 years ? factory programming available ? packages include 8-lead pdip, soic, tssop, dfn, tdfn and msop ? pb-free and rohs compliant ? temperature ranges: description: the microchip technology inc. 24c02c is a 2k bit serial electrically erasable prom with a voltage range of 4.5v to 5.5v. the device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. low-current des ign permits operation with typical standby and active currents of only 10 a and 1 ma, respectively. the device has a page write capabil- ity for up to 16 bytes of data and has fast write cycle times of only 1 ms for both byte and page writes. functional address lines allow the connection of up to eight 24c02c devices on the same bus for up to 16k bits of contiguous eeprom memory. the device is available in the standard 8-pin pdip, 8-pin soic (3.90 mm), 8-pin 2x3 dfn and tdfn, 8-pin msop and tssop packages. package types block diagram - industrial (i): -40c to +85c - automotive (e): -40c to +125c a0 a1 a2 v ss v cc wp scl sda 1 2 3 4 8 7 6 5 pdip, msop soic, tssop a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda dfn/tdfn a0 a1 a2 v ss wp scl sda v cc 8 7 6 5 1 2 3 4 i/o control logic memory control logic xdec hv generator eeprom array write-protect circuitry ydec vcc vss sense amp. r/w control sda scl a0 a1 a2 wp 2k 5.0v i 2 c ? serial eeprom
24c02c ds21202h-page 2 ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applie d ............... .............. .............. .............. ........... ........... .......... .......-40c to +125c esd protection on all pins ..................................................................................................... ................................. 4 kv ? notice : stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. ex posure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc characteristics all parameters apply across the specified operating ranges unless otherwise noted. v cc = +4.5v to +5.5v industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c parameter symbol min. max. units conditions scl and sda pins: high-level input voltage v ih 0.7 v cc ?v low-level input voltage v il ? 0.3 v cc v hysteresis of schmitt trigger inputs v hys 0.05 v cc ?v (note) low-level output voltage v ol ?0.40vi ol = 3.0 ma, v cc = 4.5v input leakage current i li ?1 av in = v ss or v cc , wp = vss output leakage current i lo ?1 av out = v ss or v cc pin capacitance (all inputs/outputs) c in , c out ?10pfv cc = 5.0v (note) t a = 25c, f = 1 mhz operating current i cc read ? 1 ma v cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v standby current i ccs ?50 av cc = 5.5v, sda = scl = v cc wp = v ss note: this parameter is periodically sampled and not 100% tested. ? 2008 microchip technology inc. ds21202h-page 3 24c02c table 1-2: ac characteristics figure 1-1: bus timing data all parameters apply across the specified operating ranges unless otherwise noted. v cc = +4.5v to +5.5v industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c parameter symbol t a > +85c -40c t a +85c units remarks min. max. min. max. clock frequency f clk ? 100 ? 400 khz clock high time t high 4000 ? 600 ? ns clock low time t low 4700 ? 1300 ? ns sda and scl rise time t r ? 1000 ? 300 ns (note 1) sda and scl fall time t f ? 300 ? 300 ns (note 1) start condition hold time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0? 0 ? ns (note 2) data input setup time t su : dat 250 ? 100 ? ns stop condition setup time t su : sto 4000 ? 600 ? ns output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of ? 250 20 + 0.1 c b 250 ns (note 1) , c b 100 pf input filter spike suppression (sda and scl pins) t sp ? 50 ? 50 ns (note 3) write cycle time t wr ? 1.5 ? 1 ms byte or page mode endurance 1m ? 1m ? cycles 25 c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoi d unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but ensured by charac terization. for endurance estimates in a specific application, please consult the total endurance? mode l which can be obtained from microchip?s web site at www.microchip.com. scl sda in t su : sta sda out t hd : sta t low t high t r t buf t aa t hd : dat t su : dat t su : sto t sp t f 24c02c ds21202h-page 4 ? 2008 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 sda serial data this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal; therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k for 100 khz, 2 k for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 2.3 a0, a1, a2 the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 24c02c devices may be connected to the same bus by using different chip select bit combina- tions. these inputs must be connected to either v cc or v ss . 2.4 wp this is the hardware write-prot ect pin. it must be tied to v cc or v ss . if tied to vcc, the hardware write protection is enabled. if the wp pin is tied to vss the hardware write protection is disabled. 2.5 noise protection the 24c02c employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 3.8 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 3.0 functional descriptions the 24c02c supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device that generates the serial clock (scl), controls the bus a ccess, and generates the start and stop conditions, while the 24c02c works as slave. both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. name pdip soic tssop dfn/tdfn msop description a0 1 1 1 1 1 address pin a0 a1 2 2 2 2 2 address pin a1 a2 3 3 3 3 3 address pin a2 v ss 44444ground sda 5 5 5 5 5 serial address/data i/o scl66666serial clock wp 7 7 7 7 7 write-protect input v cc 8 8 8 8 8 +4.5v to 5.5v power supply ? 2008 microchip technology inc. ds21202h-page 5 24c02c 4.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all opera- tions must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, alt hough only the last sixteen will be stored when doing a write operation. when an overwrite does occur it will replace data in a first-in first- out fashion. 4.5 acknowledge each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 4-2). figure 4-1: data transfer sequence on the serial bus characteristics figure 4-2: acknowledge timing note: the 24c02c does not generate any acknowledge bits if an internal programming cycle is in progress. (a) (b) (c) (d) (a) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit 24c02c ds21202h-page 6 ? 2008 microchip technology inc. 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a four bit control code; for the 24c02c this is set as ? 1010 ? binary for read and write operations. the next th ree bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24c02c devices on the same bus and are used to select which device is accessed. the chip select bi ts in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a ? 1 ? a read operation is selected, and when set to a ? 0 ? a write operation is selected. following the start condition, the 24c02c monitors the sda bus checking the control byte being transmitted. upon receiving a ? 1010 ? code and appro- priate chip select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24c02c will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1, a0 can be used to expand the contiguous address space for up to 16k bits by adding up to eight 24c02c devices on the same bus. in this case, software can use a0 of the control byte as address bit a8, a1 as address bit a9, and a2 as address bit a10. it is not possible to write or read across device boundaries. 1 0 1 0 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit ? 2008 microchip technology inc. ds21202h-page 7 24c02c 6.0 write operations 6.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit, which is a logic low, is placed onto the bus by the master transmitter. the device will acknowledge this control byte during the ninth clock pulse. the next byte transmitted by the master is the word address and will be written into the address pointer of the 24c02c. after receiving another acknowledge signal from the 24c02c the master device will transmit the data word to be written into the addressed memory location. the 24c02c acknowledges again and the master gener- ates a stop condition. this initiates the internal write cycle, and during this time the 24c02c will not gener- ate acknowledge signals (figure 6-1). if an attempt is made to write to the protect ed portion of the array when the hardware write protec tion has been enabled, the device will acknowledge the command but no data will be written. the write cycle ti me must be observed even if the write protection is enabled. 6.2 page write the write control byte, word address and the first data byte are transmitted to the 24c02c in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24c02c which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remains constant. if the ma ster should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an in ternal write cycle will begin (figure 6-2). if an attempt is made to write to the protected portion of the arra y when the hardware write protection has been enabled, the device will acknowl- edge the command, but no data will be written. the write cycle time must be observed even if the write protection is enabled. 6.3 write protection the wp pin must be tied to v cc or v ss . if tied to v cc , the upper half of the arra y (080-0ff) will be write- protected. if the wp pin is tied to v ss , then write operations to all address locations are allowed. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data n data n + 15 s t o p a c k a c k a c k a c k a c k data n +1 24c02c ds21202h-page 8 ? 2008 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally ti med write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be re-sent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow 8.0 read operations read operations are initiated in the same way as write operations with the ex ception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 8.1 current address read the 24c02c contains an address counter that main- tains the address of the last word accessed, internally incremented by one. theref ore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the 24c02c issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer, but does generat e a stop condition and the 24c02c discontinues transmission (figure 8-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24c02c as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24c02c will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c02c discontinues transmission (figure 8-2). after this command, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiat ed in the same way as a random read except that af ter the 24c02c transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24c02c to transmit the next sequentially addressed 8-bit word (figure 8-3). to provide sequential reads, the 24c02c contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address ff to address 00. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes ? 2008 microchip technology inc. ds21202h-page 9 24c02c figure 8-1: current read address figure 8-2: random read figure 8-3: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k s p s s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p bus activity master sda line bus activity 24c02c ds21202h-page 10 ? 2008 microchip technology inc. 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn 8-lead tssop example: 24c02c i/p 13f 0527 24c02ci sn 0527 13f 8-lead msop example: xxxx tyww nnn 4c2c i527 13f xxxxt ywwnnn 3 e 3 e 8-lead 2x3 dfn xxx yww nn 2p7 527 13 example: 4c2ci 52713f 8-lead 2x3 tdfn xxx yww nn ap7 527 13 example: ? 2008 microchip technology inc. ds21202h-page 11 24c02c part number 1st line marking codes tssop msop dfn tdfn i temp. e temp. i temp. e temp. 24c02c 4c2c 4c2ct 2p7 2p8 ap7 ap8 note: t = temperature grade (i, e) legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part num ber, year code, week code, and traceability code. 24c02c ds21202h-page 12 ? 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'! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & < & # %% , & & 4!! - .3 : 9& 1, : >#& . -1, .$ !# #9& - = .$ !# #>#& . = , & &>#& ) - , & &9& 9 - , & && .$ !# # c = = d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view * , -, 24c02c ds21202h-page 18 ? 2008 microchip technology inc. . $ *-,'/00%& . 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. ds21202h-page 19 24c02c . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 24c02c ds21202h-page 20 ? 2008 microchip technology inc. . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. ds21202h-page 21 24c02c appendix a: revision history revision d corrections to section 1.0, electrical characteristics. revision e added dfn package. revision f (02/2007) revised features section; section 1.0 revised ambient temperature; revised tables 1-1, 1-2, (removed com- mercial temp); revised table 2-1; replaced on-line support page; replaced package drawings; revised product id section. revision g (03/2007) replaced package drawings (rev. am). revision h (04/2008) replaced package drawings; added tdfn package; revised product id section. 24c02c ds21202h-page 22 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds21202h-page 23 24c02c the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://suppo rt.microchip.com 24c02c ds21202h-page 24 ? 2008 microchip technology inc. reader response it is our intention to provide you wit h the best documentation possible to ensur e successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to t he technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21202h 24c02c 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2008 microchip technology inc. ds21202h-page 25 24c02c product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: 24c02c 2k i 2 c? serial eeprom 24c02ct 2k i 2 c? serial eeprom (tape and reel) temperature range: i= -40 c to +85 c e= -40 c to +125 c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic, (3.90 mm body), 8-lead st = tssop (4.4 mm body), 8-lead ms = plastic micro small outline (msop), 8-lead mc = 2x3 dfn, 8-lead mny (1) = plastic dual flat (tdfn), no lead package, 2x3 mm body, 8-lead examples: a) dstemp-i/p: industrial temperature, pdip package b) dstemp-e/sn: extended temperature, soic package c) dstemp-i/mny: industrial temperature, 2x3 tdfn package note 1: ?y? indicates a nickel, palladium, gold (nipdau) finish. 24c02c ds21202h-page 26 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds21202h-page 27 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds21202h-page 28 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
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